FIG. 1 shows a block diagram illustrating a configuration of a conventional semiconductor memory device.
Referring to FIG. 1, the conventional semiconductor memory device comprises a row address input unit 20 for inputting and decoding a row address to output decoded data, a column address input unit 30 for inputting and decoding a column address to provide decoded data, a cell region unit 100 having plural cell arrays 110 to 140 with unit cells for outputting the data from the row address input unit 20 and the column address input unit 30, and a data input/output (I/O) unit 40 for transferring the data from the cell region unit 100 to the outside, or delivering data from the outside to the cell region unit 100.
The cell region unit 100 includes sense amp units 150 and 160 for amplifying the data signals from the cell arrays 110 to 140 and providing amplified signals to the data I/O unit 40. Further, each of the cell arrays 110 to 140 in the cell region unit 100 contains a plurality of unit cells.
Each sense amp functions to sense and amplify the data signals applied to the cell arrays 110 to 140 to output amplified signals to the data I/O unit 40, upon a read operation by the semiconductor memory device as mentioned above, while it serves to latch data from the data I/O unit 40 and transfer it to each cell array, upon a write operation by the device.
FIG. 2 depicts a detailed circuit diagram of the general semiconductor memory device, especially the cell array.
As shown in FIG. 2, the cell array of the semiconductor memory device is provided with plural word lines WL0, WL1, WL2, . . . , and plural bit lines BL, /BL, . . . , which intersect each other, wherein there is prepared one unit cell per an intersection point.
Each unit cell, e.g., CELL1, includes a MOS transistor M0 for conducting switch function and a capacitor C0 for storing data. The MOS transistor M0 constituting the unit cell is configured such that its gate is connected to the word line WL0, and one port to the bit line BL and the other port to the capacitor C0. And, the capacitor C0 is structured such that its one port is coupled with the other port of the MOS transistor M0, which inputs a plate voltage PL.
A pair of two unit cells CELL1 and CELL2 coupled with adjacent word lines WL0 and WL1 are commonly connected to one bit line BL and the two bit lines BL and /BL are coupled with a sense amp 152a of the sense amp unit 150 provided on one side of the cell array.
Specifically, upon a read of data on the unit cell CELL1, the word line WL0 is chosen and activated; and, thus, the MOS transistor M0 in the unit cell CELL1 is turned on and then data stored in the capacitor C0 is provided onto the bit line BL.
The bit line sense amp 152a senses and amplifies a difference of voltage levels between the bit line BL onto which data signal is applied and the bit line bar /BL onto which the data signal is not supplied.
After completing the amplification operation by the bit line sense amp 152a, the sensed and amplified data signal latched on the bit line BL is outputted to the external via external data bit lines LDB and LDBB.
At this time, the data signal is laid on the bit line BL, but its relative data is also amplified and latched on the bit line bar /BL, to provide it together with the data signal on the bit line BL in couples upon its transfer to the external of the cell array.
For example, if data “1” (indicating a state that electric charge is filled up) is stored in the capacitor C0 of the unit cell CELL1, a voltage on the bit line BL is amplified to a supply voltage level and a voltage on the bit line bar /BL is amplified to the ground voltage level. Further, if data “0” (implying a state that electric charge is discharged) is stored in the capacitor C0 of the unit cell CELL1, the voltage on the bit line BL is amplified to the ground voltage level and the voltage on the bit line bar /BL is amplified to the supply voltage level.
At this time, since an amount of the electric charge stored to indicate the data in the unit cell is very small, after using it in increasing the voltage on the bit line, the capacitor in the unit cell comes back to a state just before the discharge and then a recharging operation must be conducted in order to maintain the previous data in the capacitor continuously. Herein, the recharging operation stands for an operation to transfer the data signal latched on the sense amp to the capacitor in the unit cell and the word line is inactivated when the recharging operation has been completed.
In the meantime, upon a read of data on unit cell CELL3, the word line WL2 is activated; and, thus, the MOS transistor M2 in the unit cell CELL3 is turned on and then data stored in the capacitor C2 is applied to the bit line bar /BL. The sense amp 152a senses and amplifies a difference of voltage levels on the bit line bar /BL and the bit line BL. After the amplification operation by the sense amp 152a, the sensed and amplified data signal is outputted to the external via the external data lines LDB and LDBB. At this time, the data signal is applied to the bit line bar /BL, while a data signal with its complement level is provided to the bit line BL.
Meanwhile, in case of writing data in unit cell, a word line corresponding to the selected unit cell is activated and then data in that unit cell is sensed and amplified, as in the read operation above. After that, the sensed, amplified and latched data by the bit line sense amp 152a is replaced with data to be transferred and written from the outside.
The replaced data is latched by the bit line sense amp 152a and then the latched data is stored in the capacitor of the unit cell. If the data storage operation has been completed in the capacitor of the selected unit cell, then the word line becomes inactivated.
FIG. 3 is a configuration diagram showing a connection relationship between the sense amp and the cell array according to the prior art, particularly showing a shared bit line sense amp structure.
Referring to FIG. 3, the cell region unit 100 is provided with a multiplicity of cell arrays 100, 130 and 180 having unit cells wherein there are provided sense amp units 150 and 170 with sense amps for amplifying data between the cell arrays.
The sense amp unit 150 includes a plurality of sense amps, which correspond to the number of trine pairs coupled with one cell array.
In the shared bit line sense amp structure, since two cell arrays share one sense amp in order to decrease an area of circuit, one sense amp is sufficient for the pair of two bit lines.
Also, in case of the shared bit line sense amp structure, it is provided one sense amp unit 150 per the two cell arrays 110 and 130, in which the sense amp unit 150 and the cell arrays 110 and 130 are coupled or separated properly, based on connection signals BISH and BISL.
For instance, if a first connection signal BISH is activated, then a first connector 151 is enabled and the sense amp unit 150 is coupled with a cell array 0 110; and if a second connection signal BISL is activated, then a second connector 153 is enabled and the sense amp unit 150 is connected to a cell array 1 130.
In addition to the above connectors and the sense amps, the sense amp unit 150 further includes a pre-charge unit, a data output unit, etc., which are illustrated in FIG. 4.
FIG. 4 is a circuit diagram illustrating one embodiment of the sense amp unit shown in FIG. 2.
Referring to FIG. 4, the sense amp unit 150 comprises a sense amp 152a that is operative in response to sense amp power supply signals SAP and SAN for amplifying a difference of signals on the pair of bit lines BL and /BL, a pre-charge unit 155a that is enabled by a pre-charge signal BLEQ being provided when the sense amp 152a is not operated for pre-charging the pair of bits lines with a bit line pre-charge voltage VBLP, a first equalization unit 154a for equalizing voltage levels on the two bit lines BL and /BL connected to the cell array 0 110 in response to the pre-charge signal BLEQ, a second equalization unit 157a for equalizing voltage levels on the pair of bit lines BL and /BL connected to the cell array 1 130 in response to the pre-charge signal BLEQ, and a data output unit 156a for outputting the amplified data signal by the sense amp 152a to the outside through the data lines LDB and LDBB, in response to a column control signal YI being produced by a column address.
Further, as stated above, the sense amp unit 150 includes the first and second connectors 151a and 153a for connecting or disconnecting the sense amp 155a to or from the cell array 0 110 or the cell array 1 130.
FIG. 5 is a waveform diagram showing the operation of the conventional semiconductor memory device.
In succession, the operation of the conventional semiconductor memory device will be explained in detail with reference to FIGS. 1 to 4 below.
The semiconductor memory device is operated at intervals of pre-charge, read instruction, sense, and restore separately, upon a data read.
Further, operation and whole composition of data write process are also the same as those of the data read process except that there is a write instruction interval instead of the read instruction interval and data from the outside is latched by the sense amp in lieu of the output of data to the outside. Hereinafter, the operation of the data read will be described in detail.
First of all, in the following explanation, it is assumed that an electric charge is filled up in the capacitor. Also, it is assumed that upon a data read, the first connector 151a is enabled and the second connector 153a is disabled; and thus, the sense amp unit 150 is coupled with the first cell array 0 110.
During the pre-charge interval (Pre-charge), it is under the state that the pre-charge voltage is applied to the pair of two bit lines and that all the word lines are inactivated. A half of core voltage Vcore/2 is generally used as the pre-charge voltage (Vcore/2=VBLP).
At this interval, the pre-charge signal BLEQ is enabled at high level, and the first and the second equalization units 154a and 157a and the pre-charge unit 155a are enabled, thus making voltage levels on the pair of two bit lines maintained at Vcore/2. At this time, the first and the second connectors 151a and 153a are under the enable state.
In FIG. 5, a waveform SN indicates a voltage level applied to the capacitor in the unit cell, which represents the core voltage Vcore level because it is assumed that the data “1” is stored.
Next, at the read instruction interval (Read) where the read instruction is inputted and running, the first connector 151a maintains the enable state and the second connector 153a is in disable state. Thus, the sense amp unit 150 is connected to the cell array 0 110 arranged on its one side, while separating from the cell array 1 130 provided on its other side.
The word line WL is activated by high-voltage and is maintained up to the restore interval (Restore). At this time, the reason of applying a high voltage Vpp higher than the supply voltage onto the word line WL is to reduce loss that occurs by means of transferring the data “1” stored in the capacitor by a threshold voltage of NMOS transistor forming the unit cell onto the bit line.
In the semiconductor memory device, it is required that the supply voltage is low while the operation speed is to be more rapid. By generating the high voltage Vpp higher than the core voltage Vcore supplied to a cell region of the semiconductor memory device and using it in activating the word line WL, the word line WL can be activated at high speed.
If the word line WL is activated, the MOS transistor of the corresponding unit cell is turned on and thus the data stored in the capacitor is applied to the bit line BL.
Accordingly, the voltage on the bit line BL pre-charged with the half of core voltage Vcore/2 ascends a bit. At this time, even though the capacitor is charged with the core voltage level, the voltage on the bit line BL does not rise up to the core voltage but rises by a certain voltage ΔV from Vcore/2 since a capacitance Cc of the capacitor in the unit cell is very small compared to a parasitic capacitance Cb on the bit line BL.
As can be seen from FIG. 5, the voltage levels applied to the unit cell capacitor and onto the bit line BL ascend by the constant voltage ΔV from Vcore/2 at the read instruction interval (Read).
Meanwhile, since no further electric charge is supplied onto the bit line BL, the half of core voltage Vcore/2 is maintained.
Thereafter, during the sense interval (Sense), the first and the second driving voltages SAP and SAN, which are maintained at Vcore/2 during the pre-charge interval (Pre-charge), are supplied to the bit line sense amp 152a as the core voltage and the ground voltage, respectively. According to this, the bit line sense amp 152a senses a difference of voltages on the two bit lines BL and /BL and amplifies the differential voltage wherein it amplifies the relatively high voltage to the core voltage Vcore and the relatively low voltage to the ground voltage.
Herein, since the voltage level on the bit line BL is mainlined to be higher than that on the bit line bar /BL, the voltage on the bit line BL is replaced with the core voltage Vcore and the voltage on the bit line bar /BL with the ground voltage upon a completion of the sensing and amplifying operation.
At the following restore interval (Restore), the recharging operation is carried out since there is a discharge of the electric charge for data stored in the capacitor of the unit cell to ascend the voltage level on the bit line BL from Vcore/2 at the read interval (Read). If the recharging operation has been completed, the word line is again inactivated.
Next, referring again to the pre-charge interval, the first and the second drive voltages SAP and SAN being supplied to the sense amp are maintained at Vcore/2 and the pre-charge signal BLEQ is activated and inputted. Based on this, the first and the second equalization units 154a and 157a and the pre-charge unit 155a are activated and the pre-charge voltage VBLP is supplied to the pair of bit lines BL and /BL. At this time, the first and the second connectors 151a and 153a are activated and the sense amp 150 is connected to all of the cell arrays 110 and 130 provided on its one side and other side.
As technology develops more and more, a level of the supply voltage for driving the semiconductor memory device becomes low gradually. But, although the magnitude of the supply voltage is low, it is required that the operation speed of the semiconductor memory device is maintained as before or is to be more high.
As mentioned above, the core voltage Vcore of level lower than the supply voltage and the high voltage higher than the core voltage Vcore are created internally and used properly in the existing semiconductor memory device.
Up to now, it is possible to guarantee the required operation speed only by improving process technology of the memory device further, without a use of any specific method, though the supply voltage is decreased properly.
For example, if a level of the supply voltage is decreased to 2.5V or less from 3.3V, the required operation speed can be met in the process of gradually decreasing to 100 nm from 500 nm in manufacturing process technology. In other words, improving the process technology results in a decrease in consumption power of transistor manufactured compared to before and also more rapid operation speed than before, upon a supply of the same voltage.
However, it is very difficult to decrease the process technology further as before, under 100 nm.
Furthermore, under the situation that the required supply voltage is low to 1.5V below 2.0V, so far as 1.0V, it is very hard to maintain the operation speed as before, by the decrease of the process technology merely.
Moreover, if the level of the supply voltage supplied to the memory device is lower than a fixed level, then an operation margin of MOS transistor constituting the memory device is very small, thus making it to be not operated at the required operation speed and also lowering the reliability of operation.
Basically, under the state that a turn-on voltage of MOS transistor is maintained at a constant level, if a level of the driving voltage to the memory device falls below the constant level, it takes much time to stably sense and amplify a difference of voltages applied onto the pair of two bit lines by the bit line sense amp.
At this time, even if a little noise occurs (in case bit line voltage level rises or falls due to a little noise in the ½ core voltage), there exists an instance where the sense amp does not sense it.
Thus, decreasing the driving voltage of the memory device below the constant level is very hard under the existing technology.
Further, if the manufacturing technology of the memory device is very improved, a space between the gate polarity of MOS transistor constituting each unit cell and its adjacent bit lines becomes very small, thus incurring a leakage current between the gate polarity and the bit lines. At this time, flowing leakage current is called bleed current.
FIG. 6 is a cross-sectional view showing the problems of the conventional semiconductor memory device, especially leakage current in a low-voltage high-integrated semiconductor memory device.
FIG. 6 shows a cross-sectional view of one unit cell in the semiconductor memory device, which comprises an element isolation film 11, a source/drain conjunction regions 12a and 12b, a gate polarity 13, a bit line 17, capacitors 14 to 16, and isolation films 18 and 19, prepared on a substrate 10.
Due to the decrease in the process technology of the semiconductor memory device, an interval A between the gate polarity 13 and the bit line 17 becomes narrow gradually, making sufficient isolation difficult.
Under such state, during the pre-charge interval, the ½ core voltage is applied onto the bit line, whereas the ground voltage is supplied to the gate polarity as the word line.
Because of errors in the process, there may be a short between the bit line and the gate polarity provided as the word line; and in this case, the bleed current as the leakage current continuously flows to the word line from the bit line during the pre-charge interval.
After manufacturing the memory device, repair process is conducted, which replaces erroneous cells with spare cells prepared in advance on a word line basis, not on a unit cell basis, by considering characteristics of the memory device.
That is to say, when there is found a defect in unit cells during the operation of the memory device, spare word lines are employed instead of the corresponding word lines.
If the defect is issued due to the short between the gate polarity as the word line and the bit line, the bleed current still flows to the word line from the bit line that is under the pre-charge state by the ½ core voltage although there exists no problem by replacing with the spare word lines.
As the technology develops, it is very important issue to operate the memory device at low power. But, as long as there occurs the bleed current, such semiconductor memory device may be not employed in a system, even under an absence of the operation problem.
To decrease the bleed current, there has been evolved an idea of adding a resistor to a path in which the bleed current flows. Such idea merely reduces the bleed current somewhat but does not present any fundamental solution.
Another problem is that there is leakage current between the bit line sense amp and cell arrays that are not connected thereto.
Specifically, when a cell array is connected to the bit line sense amp for operation, other cell arrays are separated from the bit line sense amp by making a turn off of NMOS transistor provided in the connector.
At this time, bit lines of the non-connected cell arrays are maintained at the pre-charge voltage (namely, VDD/2); and in the bit line sense amp one bit line carrying the data signal is maintained at the supply voltage and the other bit lines carrying no data signal are maintained at the ground voltage.
Thus, although the MOS transistor forming the connector is turned off, the leakage current flows to the bit line sense amp from non-selected cell arrays. This is the reason that makes the operation current increased upon an access of data. Sub_Vt Leak Current shown in FIG. 4 indicates such leakage current as described above.